Optimizing VHDL Intermediate Forms – Final Report

SBIR Phase I Final Report VHDL Behavioral Synthesis Tool for Low Power Based on FRITS

Objective VHDL based Communication Design for Object- Oriented Hardware Design Final report on the OFFIS research project OO-COM (German Title: Kommunikation im objektorientierten Hardwareentwurf am Beispiel von Objective VHDL)

Digital system simulation with VHDL in a high-level synthesis system

This paper presents the use of VHDL to simulate the intermediate design representation in a high-level synthesis system. The design representation is captured by an extended time Petri net notation and is used throughout the synthesis process. We have developed an algorithm to convert the design representation into a VHDL description. As a result, digital system designs can be simulated togethe...

Optimizing VHDL code for FPGA targets

As synthesis becomes popular for generating FPGA designs, the design style has to be adapted to FPGAs for achieving optimal synthesis results. In this paper, we discuss a VHDL design methodology adapted to FPGA architectures. Implementation of storage elements, nite state machines, and the exploitation of features such as fast-carry logic and built-in RAM are discussed. Using the design style d...

High-Level Synthesis using Dependence Flow Graphs as the Intermediate Form

This paper describes an ongoing high level synthesis project using dependence ow graphs as intermediate form. This HLS system takes a behavioral description written in a subset of VHDL and generates an RTL VHDL description that implements the design. We use dependence ow graphs as an intermediate form. We only describe the compilation part of the HLS system and dependence ow graphs.